Inverter Tutorial for magic, tclspice, xcircuit &
netgen
1. Drawing the schematic with xcircuit
2. Drawing the layout with magic
3. Plotting a spice transient analysis
of the inverter from within magic using tclspice
4. Using netgen to compare the Layout Vs Schematic
(LVS)
xcircuit
To draw this circuit, invoke "xcircuit invckt"
from a shell to get a new blank page whose name
is invckt. Obtain the two transistor symbols from the library by pressing
'l' for library a couple of times until the analoglib2 library is open
with the nmos4 and pmos4 symbols. These are four terminal cmos transistors
with Drain, Gate, Source & Bulk connections suitable for a CMOS layout.
Place the two transistors on the page with the pmos transistor above the
nmos transistor.
Next, press 'l' for library again until the generic
library is open and select two circles for the input and output labels, a
vdd symbol and a gnd symbol. All of these come from the generic library. Place
them on the page as shown with the in on the left, the out on the right, vdd
on the top and gnd on the bottom. Next, press Shift-T to obtain a Text label
and set it to in. Get a second label and set it to out. Save this schematic
with File->Write XCircuit PS with the setting full page and not
emb embedded ps. Lastly, execute Netlist->Write Spice and Netlist->
Write Sim. You should have three files in your directory, invckt.ps, invckt.spc
and invckt.sim. They are all text files and be examined with a word processor,
including the schematic itself. The schematic is invckt.ps and can be downloaded
here. The sim file should
have two transistors in it and look like this:
The spice file is shown below, where the first
line indicates a p transistor with the Gate connected to in, the Drain connected
to out and the Source connected to Vdd. The second line indicates an n
transistor with the Gate connected to in, the Drain connected to out and
the Source connected to GND. This file can be plotted with spice and should
have a similar result to a spice file extracted directly from the magic
layout.
*SPICE circuit <invckt> from XCircuit v3.10
M1 out in Vdd Vdd pmos W=3u L=2u
M2 out in GND GND nmos W=3u L=2u
.end
And this is the .sim circuit of the inverter. It has a
simpler format with just the gate, source and drain. The bulk connection is not shown in the sim file, but it is shown
in the spice file along with the Width and Length of each transistor in
microns. This is the one that netgen will be used
with for LVS.
| sim circuit "invckt" from XCircuit v3.10
p in out Vdd
n in out GND
We are next going to draw this same inverter using magic and use its
capabilities to create a similar .sim and .spice file and get to comparing
them a little bit later to ensure the inverter as drawn matches the schematic
as drawn.
magic
To draw the layout of the inverter, invoke "magic -w invlay" from a shell
to get the tcl console and a new magic layout window. At this point you need
to place an nwell at the top, a pwell at the bottom, metal1 for Vdd and
GND at both top and bottom, pdiff which is 3 lambda &pdc on the top,
ndiff which is 3 lambda wide & ndc on the bottom, poly which is two
lambda wide for each gate and draw the poly out to the left and form the
in connection.
At this point, you should have a complete layout,
select the topmost cell in the window by drawing a box around the whole thing
and pressing s and then with the tcl console, do:
;save invlay
;extract all
;exttosim rthresh infinite
;exttosim cthresh infinite
;exttospice
Now, there should be several new files. These would be invlay.mag, .sim,
.ext, and .spice. The layout itself is the .mag file. The reason that exttosim
was invoked twice was to get all the resistors of any value (exttosim rthresh
infinite) and all of the capacitors of any value (exttosim cthresh infinite).
The .spice file should look similar to the schematic file as shown below with
first the .sim file and second the .spice file. The layout is invlay.mag and
can be downloaded here.
Here you can see the .spice file has M1000 connected with
DGSB (Drain, Gate, Source, Bulk) in the same manner as the schematic and
it is the pfet. The differences are the source and drain are reversed. CMOS
layouts are symmetrical in that the source and drains can be interchanged
with no harm to the circuit. It works either way. The second difference is
the model pfet instead of pmos and nfet instead of nmos. The third difference
are the 5 capacitors. They represent the parasitic capacitances of the circuit
as extracted from the layout in femto-farads.
* SPICE3 file created from invlay.ext - technology: scmos
M1000 Vdd in out Vdd pfet w=3u l=2u
+ ad=19p pd=18u as=19p ps=18u
M1001 out in GND GND nfet w=3u l=2u
+ ad=19p pd=24u as=19p ps=24u
C0 GND in 6.3fF
C1 in Vdd 6.0fF
C2 out GND 2.0fF
C3 GND GND 5.3fF
C4 Vdd GND 5.5fF
This is the simulation file. It has some parasitics and
the resistances of the nodes.
| units: 100 tech: scmos format: SU
p in out Vdd 2 3 8 13 g=S_Vdd s=A_19,P_18 d=A_19,P_18
n in GND out 2 3 8 -16 g=S_GND s=A_19,P_24 d=A_19,P_24
C out GND 2.0
C in GND 6.3
C in Vdd 6.0
R out 243
R in 418
C GND GND 5.3
R GND 204
C Vdd GND 5.5
R Vdd 3423
Here you can see the .spice file has M1000 connected
with DGSB (Drain, Gate, Source, Bulk) in the same manner as the schematic
and it is the pfet. The differences are the source and drain are reversed.
CMOS layouts are symmetrical in that the source and drains can be interchanged
with no harm to the circuit. It works either way. The second difference is
the model pfet instead of pmos and nfet instead of nmos. The third difference
are the 5 capacitors. They represent the parasitic capacitances of the circuit
as extracted from the layout in femto-farads.
tclspice
In order to do the spice analysis from within magic using
tcl, we need a circuit to provide power, a pulse generator, nmos/pmos models
and include the spice file extracted from magic. Here is such a circuit
and it can be downloaded here.
* CMOS Inverter power and pulse generator
*include the magic extracted spice file
.include invlay.spice
*Place a modest load capacitor and a resistor to connect GND to 0
Cload out 0
0.1P
Rgnd GND 0
0.001
*Now we need a 3.3V power supply
VCC vdd 0
DC=3.3
*And next a pulse generator
*Vname +Node -Node Option T1 V1 T2 V2
T3 V3 T4 V4 T5 V5
Vin in 0
PWL( 0 0 8N 0
8.2N 3 16N 3 16.2N 0 )
*Define the step size and duration of the spice run
.TRAN 0.1N 25N
*Tell it not to be too hot or too cold
.OPTIONS TEMP=25 METHOD=GEAR
*and finally a couple of models to bring nfet to nmos and pfet to pmos
*MODEL NAME TYPE
.MODEL nfet NMOS (level=2 LD=0.15U TOX=200.0E-10 NSUB=5.37E+15
+ VTO=0.74 KP=8.0E-05 GAMMA=0.54 PHI=0.6 U0=656 UEXP=0.157 UCRIT=31444
+ DELTA=2.34 VMAX=55261 Xj=0.2U LAMBDA=0.037 NFS=1E+12 NEFF=1.001 NSS=1E+11
+ TPG=1.0 RSH=70.00
+ CGDO=4.3E-10 CGSO=4.3E-10 Cj=0.0003 Mj=0.66
+ CJSW=8.0E-10 MJSW=0.24 PB=0.58
.MODEL pfet PMOS (level=2 LD=0.15U TOX=200.0E-10 NSUB=4.33E+15
+ VTO=-0.74 KP=2.70E-05 GAMMA=0.58 PHI=0.6 U0=262 UEXP=0.324 UCRIT=65720
+ DELTA=1.79 VMAX=25694 Xj=0.25U LAMBDA=0.061 NFS=1E+12 NEFF=1.001 NSS=1E+11
+ TPG=1.0 RSH=121.00
+ CGDO=4.3E-10 CGSO=4.3E-10 Cj=0.0005 Mj=0.51
+ CJSW=1.35E-10 MJSW=0.24 PB=0.64
.END
Notice that the magic spice file for the inverter is included. This is
because magic doesnt have pulse generators, power supplies or models. These
two models are somewhat generic and are used merely to demonstrate the functionality
of the software. The actual model used is determined by the IC process to
be simulated. Basically a test circuit like this can be used to test many
different types of simple cells with little or no modification.
Now we are going to load the magic inverter file "invlay", create an
.ext file with extract, a .sim file with exttosim and a .spice file with
exttospice. The following steps are used to generate thise file and then
to run spice and plot the input and output of our inverter when stimulated
by a pulse using tclspice from within magic:
;load invlay
;extract all
;exttosim
;exttospice
;load /usr/lib/libspice
;spice::source testx_trans.cir
;spice::run
;plot in out
Note that it is important at this point to invoke plot like the above line.
There is a plot in magic and it is invoked as "magic::plot postscript <file>"
and plots the layout as a postscript file. The issue is that "spice::plot
in out" doesnt work at this time.
This gives you a transient plot of the input and output of the inverter
using tclspice. This plot was done entirely inside magic. Below is a screen shot of the tclspice plot output from the
files described above. The blue line in the graph in the bottom right corner
is the pulse input as described by the PWL pulse generator statement in the
testx_trans.cir spice file. This is connected to the input of the inverter.
The red line in the same graph is the output of the inverter and shows the
rise and fall times of the transistors modeled from the layout including
the parasitic capacitances from the various layers on the silicon.
netgen
At this point we are trying to compare the .sim file from
the schematic invckt.sim
and the sim file from the layout invlay.sim. The procedure
is to invoke the tcl console tkcon with netgen. At that point, type "lvs invckt
invlay". We are also going to delate the extracted R's and C's so as not
to have to put them back into the schematic. The point here is to determine
transistor connectivity and LVS. It is certainly possible (and some might
say recommended) to put the extracted capacitors and resistors into the schematic,
in this case, we deleted them. Here is the output:
loading history file ... 48 events added
Running Console Functions
Netgen 1.1 compiled on Sat Mar 29 12:08:18 EST 2003
Warning: netgen command 'run' use fully-qualified name '::netgen::run'
Main console display active (Tcl8.3.3 / Tk8.3.3)
(root) 49 % readnet spice invckt.spc
Ignoring line starting with token: .end
line number 5 = '.end'
(root) 50 % readnet spice invlay.spice
(root) 51 % compare
wrong # args: should be "compare cell1 cell2"
(root) 52 % compare invckt.spc invlay.spice
Contents of circuit 1: Cell: 'invckt.spc'
Cell invckt.spc contains 2 instances.
Class: n
instances: 1
Class: p
instances: 1
Cell contains 4 nodes.
Contents of circuit 2: Cell: 'invlay.spice'
Cell invlay.spice contains 2 instances.
Class: n
instances: 1
Class: p
instances: 1
Cell contains 4 nodes.
Circuit 1 contains 2 elements, Circuit 2 contains 2 elements.
Circuit 1 contains 4 nodes, Circuit 2 contains 4 nodes.
Iteration: 0: Element classes = 2 (+2);
Node classes = 2 (+2)
(root) 53 % permute
n-channel: source == drain.
p-channel: source == drain.
poly cap: permuting poly1 regions.
resistor: permuting endpoints.
capacitor: permuting sides.
(root) 56 % netgen::run converge
Iteration: 1: Element classes = 2 (+0);
Node classes = 4 (+2)
Circuits match uniquely.
Iteration: 2: Element classes = 2 (+0);
Node classes = 4 (+0)
(root) 57 % verify
Circuits match uniquely.
(root) 58 %